Many chip interfaces use differential signaling, such as Low-Voltage Differential Signaling (LVDS), for high-speed signal transmission such as multi gigahertz applications as an example. However, most internal chip circuit functions are implemented using full CMOS logic type signals. Therefore, translation circuits for converting differential signals into CMOS logic signals are required. In addition, many chips use differential logic for high-speed internal signals, and CMOS logic for lower speed internal signals. The conversion between these types of signals on-chip also requires translation circuits. Differential logic generally includes situations where two signal lines, typically complements of each other, are used to represent a single logic value, as opposed to one signal line.
FIG. 1 illustrates a conventional architecture 20 for differential to CMOS level translation. In FIG. 1, the architecture for translation relies on an amplifier core 22, augmented by a current-mirroring scheme 24, and a CMOS buffer 26 to output the signal in full CMOS levels. FIG. 2 shows a circuit implementation 30 according to this conventional architecture.
In FIG. 2, as differential inputs in_p and in_n switch, the current is switched between the left and right legs of the differential pair. Depending on which of the two inputs is higher, current can be sourced by either transistors M3 or M4. If through transistor M3, the current is mirrored through transistors M5, M7, and then M8 (current path B as shown by a dashed line). If through transistor M4, then it is mirrored through transistor M6 (current path A as shown by a dashed line). Transistors M6 and M8 constitute the output stage of the translator. As a result, the node x is either charged up through M6 (if in_n>in_p), or discharged through M8 (if in_p>in_n). The voltage drops across transistors M6 and MB are usually minimized to bring the value of node x as close as possible to the rails, as formed by supply VDD and ground VSS. This can ensure that the output inverter is tripped correctly.
The above architecture 30 suffers from a few disadvantages. One such disadvantage is that unequal current switching paths can lead to jitter in timing. If the current switching follows a longer path for one logic value (e.g., node x discharging) and not the other (e.g., node x charging) then it takes longer for the translator to output that logic value. Of course, there are many current-switching schemes that can overcome this problem. However, most such approaches add devices to the circuit. Adding more devices to equalize the current paths can lead to additional capacitance in the circuit, thus decreasing the circuit's bandwidth.
Another disadvantage is that node x is a high-impedance node, due to the saturation resistances of transistors M6 and M8, which are generally large. This means that slight changes in current through those two transistors can lead to large voltage changes at node x. In turn, the voltage at node x is not well controlled. Mismatch between transistors M6 and M8 would also significantly affect the voltage value of node x. Of course, it is impossible to match M6 and M8 over all process corners, which means that node x is, in practice, not well controlled.
Another disadvantage of this conventional approach 30 is that variations in transistor performance over process, voltage, and temperature (PVT) corners can lead to varying jitter performance. Even if relatively low jitter can be achieved by matching transistors in the amplifier section and in the output inverter for one corner, the matching would no longer be applicable if the transistor silicon performance changed due to process variations or if operating environment parameters changed.
As recognized by the present inventors, what is needed is a high-speed differential logic to CMOS logic translator architecture, outputting signals with low rise/fall time skew. It is against this background that embodiments of the present invention have been developed.